1. Field of the Invention
The present invention relates to an electronic system with a self-test function capable of evaluating operation results of a tested circuit, and a simulation system of the electronic system capable of simulating the operation of the electronic system.
2. Description of Related Art
FIG. 23 is a block diagram showing a configuration of a conventional electronic system with a self-test function. In FIG. 23, the reference numeral 1 designates a pseudo-random test pattern generator for serially outputting data constituting a pseudo-random test pattern; 2 designates a scan-path circuit that acquires a pseudo-random test pattern by loading the data serially output from the pseudo-random test pattern generator 1, and supplies a logic circuit to be tested (simply called xe2x80x9ctested circuitxe2x80x9d from now on) 3 with the pseudo-random test pattern in parallel, and that loads an operation result of the tested circuit 3 in parallel, and serially outputs data constituting the operation result; 3 designates the tested circuit that receives from the scan-path circuit 2 the pseudo-random test pattern in parallel, executes predetermined logical operations based on the pseudo-random test pattern, and supplies the scan-path circuit 2 with the operation result in parallel; 4 designates a signature register that loads the data serially output from the scan-path circuit 2, and compresses the operation result; and 5 designates a controller for controlling the pseudo-random test pattern generator 1, scan-path circuit 2 and signature register 4.
FIG. 24 is a block diagram showing a configuration of the pseudo-random test pattern generator 1. In FIG. 24, the symbol XOR designates an exclusive-OR circuit; and G0-G4 each designate a flip-flop with a hold function, which holds its data when HOLDG=1, and shifts the data when HOLDG=0. Here, the pseudo-random test pattern generator 1 of FIG. 24 is an LFSR (Linear Feedback Shift Register) type circuit.
FIG. 25 is a block diagram showing a configuration of the scan-path circuit 2. In FIG. 25, symbols SFF0-SFFnxe2x88x921 each designate a scan flip-flop which carries out a serial shift operation when SM=1, and a parallel input operation from the D terminal when SM=0. Here, the scan flip-flops SFF0-SFFnxe2x88x921 consists of a selector and a flip-flop.
FIG. 26 is a block diagram showing a configuration of the signature register 4. In FIG. 26, the symbol XORF and XOR3 each designate an exclusive-OR circuit; and SO-S3 each designate a flip-flop with a hold function, which holds its data when HOLDS=1, and shifts the data when HOLDS=0. Here, the signature register 4 of FIG. 26 is an FSR (Feedback Shift Register) type circuit.
Next, the operation of the conventional electronic system with a self-test function will be described.
The electronic system with a self-test function executes the evaluation of the operation of the tested circuit 3 through the following roughly divided four processings.
(1) Set initial patterns to the pseudo-random test pattern generator 1, scan-path circuit 2 and signature register 4.
To prevent undefined operation of the electronic system, a processing is carried out first for setting initial values to the flip-flops G0-G4 in the pseudo-random test pattern generator 1, to the scan flip-flops SFF0-SFFnxe2x88x921 in the scan-path circuit 2, and to the flip-flops S0-S3 in the signature register 4. The setting of the initial values are carried out by the controller 5 or by an initializing circuit not shown.
(2) Supply the pseudo-random test pattern from the scan-path circuit 2 to the tested circuit 3 in parallel, and feed the operation result back from the tested circuit 3 to the scan-path circuit 2 in parallel (the initial pattern, which is supplied as the pseudo-random test pattern at the first time, may be other than a pseudo-random test pattern).
Holding the pseudo-random test pattern, the scan-path circuit 2 supplies the tested circuit 3 with values held by the scan flip-flops SFF0-SFFnxe2x88x921 from their Q terminals.
Thus, the tested circuit 3 receives from the scan-path circuit 2 the pseudo-random test pattern in parallel, executes the logical operation in accordance with the pseudo-random test pattern, and supplies the operation result to the scan-path circuit 2 in parallel.
Since the controller 5 places SM at xe2x80x9c0xe2x80x9d in this case, the scan-path circuit 2 captures in parallel through the D terminals the operation result output from the tested circuit 3, and stores the data constituting the operation result into the scan flip-flops SFF0-SFFnxe2x88x921.
At this stage, since the controller 5 places the HOLDG and HOLDS at xe2x80x9c1xe2x80x9d, the pseudo-random test pattern generator 1 and scan-path circuit 2 hold the data rather than shift the data.
(3) Execute n-time shift operation of the pseudo-random test pattern generator 1, scan-path circuit 2 and signature register 4 (where n is the number of stages of the scan-path circuit 2).
The pseudo-random test pattern generator 1 serially supplies from the SOG terminal to the scan-path circuit 2 the data constituting the pseudo-random test pattern. More specifically, when the controller 5 places the terminal HOLDG at xe2x80x9c0xe2x80x9d after the initial set of the flip-flops G0-G4 in the pseudo-random test pattern generator 1, the pseudo-random test pattern generator 1 starts receiving a clock signal, and shifts its data in synchronism with the clock signal. For example, when the initial values xe2x80x9c11111xe2x80x9d are set to the flip-flops G0-G4, (see, STATE 0 of FIG. 27), the values stored in the flip-flops G0-G4 vary as shown in FIG. 27 every time the clock pulse is supplied, and the value stored in the flip-flop GO is serially supplied to the scan-path circuit 2.
Since the controller 5 sets SM of the scan-path circuit 2 at xe2x80x9c1xe2x80x9d in this state, the scan-path circuit 2 serially loads through the SI terminal the data constituting the pseudo-random test pattern serially output from the pseudo-random test pattern generator 1 (the value stored in the flip-flop G0) in response to the clock signal, and stores the data into the scan flip-flop SFFnxe2x88x921. At the same time, the scan flip-flops SFF0-SFFnxe2x88x921 each shift their data to their right neighboring scan flip-flops. Thus, the data held by the scan flip-slop SFF0 is serially supplied to the signature register 4 every time the clock pulse is supplied.
The shift operation, which is carried out by the number of stages of the scan-path circuit 2, is completed when the data previously loaded into the scan flip-flop SFFnxe2x88x921 by the parallel input of the operation result from the tested circuit 3 (the foregoing processing (2)) is transferred to the signature register 4.
At the same time that the shift operation is completed, the tested circuit 3 completes the output of the operation result, and the scan flip-flops SFF0-SFFnxe2x88x921 complete the storing of the data constituting the pseudo-random test pattern.
Because the controller 5 sets the signal HOLDS at xe2x80x9c0xe2x80x9d in this state, the signature register 4, receiving the clock signal, serially loads through the SIS terminal the data constituting the operation result of the tested circuit 3, which is output from the scan flip-flop SFF0 of the scan-path-circuit 2. Receiving the data constituting the operation result, the signature register 4 compresses the data by carrying out the shift operation in synchronism with the clock signal, thereby compressing the n-bit operation result into 4-bit data. Thus, the values stored in the flip-flops S0-S3 become the operation result when the shift operation has been iterated n times.
(4) Repeat the foregoing processings (2) and (3) (mxe2x88x921) times.
The scan-path circuit 2 sequentially supplies the tested circuit 3 with (mxe2x88x921) pseudo-random test patterns following the initial pattern in parallel, and acquires the operation result of the tested circuit 3 in parallel (mxe2x88x921) times, thereby successively stores the compression results of the total of m operation results (including the logical operation result based on the initial pattern) in the flip-flops S0-S3 of the signature register 4. The go/no-go decision of the electronic system is made by an external test instrument that compares the values stored in the flip-flops S0-S3 of the signature register 4 with expected values.
With the foregoing configuration, the conventional electronic system with a self-test function has a problem of taking a long time to evaluate the operation results because the processings (2)-(4) require (1+n)xc3x97m clock cycles to evaluate the operation results of the m-time logical operations by the tested circuit 3 (which will be referred to as xe2x80x9clogical simulationxe2x80x9d from now on).
Furthermore, to execute a fault simulation to obtain a fault detection rate, the logical simulation must be iterated multiple times (for example, k times), which means that the total of (1+n)xc3x97mxc3x97k clock cycles is required.
Accordingly, in the state of the art, the logical simulation entails a considerable cost (such as computer cost).
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide an electronic system with a self-test function capable of evaluating the logical operation of a tested circuit by using a simulation system, which can execute the logical simulation in a less clock cycles, rather than by activating an actual circuit.
Another object of the present invention is to provide a simulation system of the electronic system, which can evaluate the logical operation of a tested circuit mounted on the electronic system in a short time.
According to a first aspect of the present invention, there is provided an electronic system with a self-test function comprising: a pseudo-random test pattern generator for serially outputting data constituting a pseudo-random test pattern; a scan-path circuit for capturing the pseudo-random test pattern by receiving the data serially output from the pseudo-random test pattern generator, for supplying the pseudo-random test pattern in parallel to a tested circuit, for receiving in parallel an operation result of the tested circuit, and for serially outputting data constituting the operation result; a data compression circuit for compressing the operation result by receiving the data serially output from the scan-path circuit; and a memory for storing, when the pseudo-random test pattern generator begins to serially output the data constituting the pseudo-random test pattern, a 1-bit shifted pseudo-random test pattern that is obtained by shifting the pseudo-random test pattern by one bit, wherein the pseudo-random test pattern generator serially supplies the scan-path circuit with data constituting the 1-bit shifted pseudo-random test pattern when the scan-path circuit loads the operation result of the tested circuit in parallel.
Here, the electronic system with a self-test function may further comprise a comparator for comparing the operation result compressed by the data compression circuit with expected values.
The data compression circuit may comprise an exclusive OR circuit and a serial shift register, wherein the exclusive OR circuit receives data output from a final stage of the serial shift register and data serially output from the scan-path circuit, and supplies an initial stage of the serial shift register with data output from the exclusive OR circuit.
The scan-path circuit may comprise a greater number of flip-flops than a number of output terminals of the tested circuit, from which the operation result is output in parallel, and each of the flip-flops not connected to the output terminals of the tested circuit may load a fixed value when the scan-path circuit loads the operation result of the tested circuit in parallel.
The electronic system with a self-test function may further comprise, between the scan-path circuit and the data compression circuit, a gate circuit for placing the serial output of the scan-path circuit at a fixed value when the scan-path circuit comprises a greater number of flip-flops than a number of output terminals of the tested circuit, from which the operation result is output in parallel.
According to a second aspect of the present invention, there is provided a simulation system of an electronic system comprising: a virtual scan-path circuit including a serial shift register with a number of stages identical to a number of stages of a scan-path circuit of the electronic system, the virtual scan-path circuit shifting, every time the serial shift register supplies a pseudo-random test pattern in parallel to a tested circuit, the pseudo-random test pattern by one bit; a logic circuit including an identical number of exclusive OR circuits to a number of stages of a data compression circuit of the electronic system, the exclusive OR circuits carrying out logical operations between data constituting an operation result output from the tested circuit when the virtual scan-path circuit supplies the pseudo-random test pattern in parallel to the tested circuit; and a virtual data compression circuit for compressing the operation result of the tested circuit by receiving in parallel logical operation results by the logic circuit.
Here, the virtual data compression circuit may comprise, when the number of stages of the scan-path circuit equals N xc3x97Mxc2x11, where N is an integer and M is the number of stages of the compression circuit, M exclusive OR circuits and M flip-flops alternately connected in series, and the exclusive OR circuits in the virtual data compression circuit may receive data output from the exclusive OR circuits constituting the logic circuit and data output from previous and final stage flip-flops in the virtual compression circuit, and supply logical operation results of the exclusive OR circuits in the virtual data compression circuit to subsequent flip-flops in the virtual data compression circuit.
The virtual data compression circuit may comprise, when the number of stages of the scan-path circuit equals Nxc3x97M, where N is an integer and M is the number of stages of the compression circuit, M exclusive OR circuits, and the exclusive OR circuits in the virtual data compression circuit may receive data output from the exclusive OR circuits constituting the logic circuit and data output from post-stage flip-flops in the virtual data compression circuit, and supply logical operation results of the exclusive OR circuits in the virtual data compression circuit to subsequent lip-flops in the virtual data compression circuit.